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Retym
Open roleUpdated>14 days

Mixed-Signal Verification Team Lead

RetymRamat-Gan (Tel-Aviv area)
Work model
Hybrid
Experience
8+ years
Employment
Full Time
Compensation
Not disclosed
Technology signal
3 tags

Technology context

3

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VerilogSystemVerilogUVM

Full listing

Role description

Description

For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Mixed signal verification Tean-Lead.

Requirements

  • Lead and manage a distributed team of mixed-signal verification engineers across different time zones, ensuring smooth communication and collaboration.
  • Collaborate with analog and digital design teams to establish specifications, verification plans, and key milestones.
  • Define and oversee the development of behavioral models (BM) of analog designs, integrating them into digital verification flows.
  • Drive the execution of mixed-signal dynamic verification using industry-standard digital verification tools (excluding AMS).
  • Debug and resolve complex issues in mixed-signal designs, ensuring functionality and specification compliance.
  • Plan and implement scalable and reusable verification environments using Verilog/SystemVerilog.
  • Provide mentorship and technical guidance to team members, supporting their professional growth.
  • Manage project timelines, resource allocation, and reporting to ensure successful delivery of verification goals.

Minimum Qualifications

  • 8+ years of experience in mixed-signal and/or digital mixed signal verification.
  • 3+ years of experience managing or leading verification teams.
  • Proven experience in Behavioral Modeling (BM) of analog designs for digital verification.
  • Expertise in mixed-signal dynamic verification using digital verification tools (excluding AMS).
  • Knowledge Verilog/SystemVerilog for building and debugging testbenches.
  • Experience with Virtuoso for analog schematic understanding and review.
  • Solid understanding of analog design fundamentals and concepts.

Preferred Qualifications

  • Hands-on experience with UVM methodology.
  • Proficiency in both Synopsys or Cadence verification tools.

Additional Skills

  • Verification Methodologies and Tools : Proven ability to develop scalable, portable test cases and utilize verification tools effectively, including simulators, waveform viewers, and coverage collection.
  • Collaborative Environment : Experience verifying analog/mixed-signal designs in a cross-functional, team-oriented setting.
  • Communication : Exceptional skills in writing test plans, presenting results, and communicating effectively with multi-disciplinary teams and stakeholders.