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Retym
Open roleUpdated>14 days

VLSI Design Engineer

RetymRamat-Gan (Tel-Aviv area)
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Work model
Hybrid
Experience
5+ years
Employment
Full Time
Compensation
Not disclosed
Technology signal
8 tags

Technology context

8

Parsed from the vacancy text; ordered by relevance to this role.

PythonASICVerilogSystemVerilogDFTFPGAEthernetPerl

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Role description

Description

We are looking for talented and experienced VLIS Design Engineers/Micro-architects.

As an VLIS Design Engineer/Micro-architect, you'll have the opportunity to design highly sophisticated, innovative new cutting edge communication systems from scratch.

In this position you will be responsible for coming up with creative solutions to architectural challenges and crafting the very fine details of the implementation

Requirements

Job requirements

  • 5 years of experience as ASIC/FPGA designer
  • Strong Verilog/System-Verilog experience
  • Familiar with simulation tools/environments, verification methodologies
  • Strong team player, solid interpersonal skills
  • Entrepreneurial can-do attitude, self-motivated, able to work independently
  • BS/MS in EE/CE from lead universities

Background in one or more of the following domains is an advantage:

  • Familiar with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
  • Design DSP of oriented blocks
  • Ethernet (100G and above)
  • Scripting experience using several of the following: Python, Perl, TCL