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Google
Open role>1 month

Physical Design Engineer, FullChip/ASIC Implementation

GoogleMountain View, CA, United States
Work model
Office
Experience
4+ years
Employment
Full Time
Compensation
138,000 – 197,000 USD
Technology signal
4 tags

Technology context

4

Parsed from the vacancy text; ordered by relevance to this role.

ASICVerilogSystemVerilogPerl

Published salary bands

Each level keeps its own disclosed range. Amounts are not merged across levels or locations.

  • Band 1

    138,000–197,000 USD / year

    Period inferred from amount; verify against the original listing.

Full listing

Role description

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google .

Responsibilities

  • Develop all aspects of ASIC RTL2GDS implementation for high Performance, Power, Area (PPA) designs.
  • Manage full-chip level physical implementation.
  • Define and implement innovative schemes to improve performance and power.
  • Work with cross-functional teams to deliver best quality of results.

Minimum qualifications

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 4 years of experience in physical design.
  • Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
  • Experience in high-performance synthesis, PnR, sign-off convergence, including STA and sign-off optimizations.

Preferred qualifications

  • Experience in top-level floorplanning and block integration.
  • Experience in low power design implementation including UPF/CPF, multi-voltage domains and power gating.
  • Experience with ASIC design flows and methodology of physical design.
  • Understanding of circuit design, device physics, and deep submicron technology.
  • Knowledge of Verilog/SystemVerilog and fundamentals of computer architecture.
  • Effective skills with scripting languages such as Tcl, or Perl.