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NextSilicon
Open role>1 month

Senior Design Engineer-CPU

NextSiliconIsrael
Work model
Office
Experience
6+ years
Employment
Not specified
Compensation
Not disclosed
Technology signal
5 tags

Technology context

5

Parsed from the vacancy text; ordered by relevance to this role.

AlgorithmsASICFrontendSoftware ArchitectureFPGA

Full listing

Role description

Description

NextSilicon is a swiftly growing unicorn startup that is reimagining high-performance computing. Our pioneering RISC-V and accelerator coprocessor vastly accelerates supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC and AI to fulfill its promise of breakthroughs in all advanced research fields.

At NextSilicon, everything we do is guided by three core values:

  • Professionalism : We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
  • Unity : Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
  • Impact : We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.

We are looking for an experienced, talented CPU ASIC front-end design expert and technical lead. In this role, you will take part in developing cutting-edge high performance best in class RISC-V CPU, from definition stage through planning stage and the development of new features while solving challenging implementation problems and ending in successful tape-out and product bring-up .

Requirements

  • 6+ years of experience in complex ASIC designs
  • VLSI expert with a deep understanding of chip architecture and design flows
  • Excellent interpersonal skills, able to drive colleagues to achieve the project goals
  • Experience in design for timing and power
  • Experience working with various front-end tools and flows (CDC, LINT, Synthesis, etc)
  • Experience in high frequency or CPU design - an advantage

Responsibilities

  • Learn high performance RISC-V Arch and algorithms
  • Define and drive the design of advanced and super complexed blocks from micro-architecture phase to tape out.
  • Work closely with various teams to drive execution (SW, Architecture, verification, BE, FPGA, postSi etc)
  • Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making