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4 vacancies found

Senior DFT Methodology - Data Analytics and Applied AI EngineerHybrid
Full Time1+ yearsSeniorData & AI
NVIDIANVIDIA
US, CA, Santa Clara
Sr Hardware Manager, (Board Design and Signal Integrity (SI) )Office
ManagerHardware & Manufacturing
Palo Alto NetworksPalo Alto Networks
Santa Clara, CA, United States
APTM Yield Analysis/Device EngineerHybrid>14 days
Full Time5+ yearsEngineering
IntelIntel
US, New Mexico, Albuquerque
Senior Physical Design Methodology Engineer, Innovus FlowsHybrid>14 days
Full Time25+ yearsSeniorHardware & Manufacturing
NVIDIANVIDIA
US, CA, Santa Clara; US, TX, Austin; Remote